1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device characterized in that a part of basic timings of operations of an internal memory cell array is asynchronous with the outside.
2. Description of the Background Art
In recent years, a memory of a large capacity is in demand conspicuously as a portable electronic device such as a portable telephone has more and more functionality.
As a memory of such a device, generally, a static random access memory (SRAM) is mainly used. In the case of realizing a memory of a large capacity by this SRAM, the cost of the memory forms a large proportion of the whole system. In order to avoid an increase in price of the device, therefore, an idea of using a dynamic random access memory (DRAM) of a low cost per unit bit of the memory in place of an SRAM has been generated.
For manufacturers of portable electronic devices each using an SRAM as a main memory of a system, it is difficult to newly assemble a control circuit of a refreshing operation into the system. Consequently, manufacturers have been being developing a new memory using a memory cell that is used in a dynamic random access memory but capable of transmitting/receiving data to/from the outside by a control similar to that of an SRAM.
To be specific, the memory is characterized in that a dynamic memory cell as employed in a DRAM is used as an internal memory cell, an external interface substantially the same as that in an SRAM is used, refreshing operation is controlled internally by the chip itself, and refreshing control does not have to be particularly performed from the outside.
In the specification, in the connection with the function, such a memory will be called a DRAM with a complete hidden refresh function.
FIG. 8 is a block diagram showing the configuration of a conventional DRAM 501 with the complete hidden refresh function.
Referring to FIG. 8, DRAM 501 with the complete hidden refresh function includes: an input terminal group 2 for receiving controls signals /CE, /OE, /WE, /LB, and /UB; a terminal group 4 to/from which data signals DQ0 to DQ7 are input/output; a terminal group 6 to/from which data signals DQ8 to DQ15 are input/output; a terminal group 8 to which address signals A0 to An are input; a power supply terminal 10 to which a source potential VCC is supplied; and a ground terminal 12 to which a ground voltage GND is applied.
Control signal /CE is a chip enable signal for selecting DRAM 501 when DRAM 501 is accessed from the outside. Control signal /OE is an output enable signal for setting DRAM 501 into a read mode and making an output buffer active. Control signal /WE is a write enable signal for setting DRAM 501 into a write mode. Control signal /LB is a signal for making selection of inputting/outputting data from/to data terminal group 4 on a lower-bit side. Control signal /UB is a signal for making selection of inputting/outputting data from/to data terminal group 6 on an upper-bit side.
DRAM 501 further includes: a mode control circuit 14 for receiving the signals from input terminal group 2 and address signals A0 to An and detecting a refresh stop mode; a refresh trigger generating circuit 16 for generating a refresh trigger signal REFCYC in accordance with an output of mode control circuit 14; and a control clock generating circuit 522 for outputting a control clock corresponding to a predetermined operation mode to each block in accordance with the signals supplied from input terminal group 2 and refresh trigger signal REFCYC.
DRAM 501 further includes: a column address buffer 24 for receiving address signals A0 to Am (where m denotes a natural number smaller than n) and transmitting them to the inside in accordance with an output of control clock generating circuit 522; and a row address buffer 25 for receiving address signals Am+1 to An and transmitting them to the inside in accordance with an output of control clock generating circuit 522.
DRAM 501 further includes: a row decoder 26 for receiving internal address signals IAm+1 to IAn output from row address buffer 25 in accordance with an output of control clock generating circuit 522 and selecting a word line WL; a column decoder 28 for receiving internal address signals IA0 to IAm output from column address buffer 24 in accordance with an output of control clock generating circuit 522 and selecting a bit line BL; a memory cell array 32 including memory cells MC arranged in a matrix; and a sense amplifier band 30 for amplifying and reading an output of memory cell array 32. Sense amplifier band 30 includes, but not shown, a plurality of sense amplifiers and a plurality of input/output circuits.
In FIG. 8, one word line WL, one bit line BL, and one memory cell MC out of the plural memory cells MC included in memory cell array 32 are shown representatively.
DRAM 501 further includes: a lower-bit side input buffer IBL for receiving data signals DQ0 to DQ7 from terminal group 4 in accordance with a lower-bit control signal LC output from control clock generating circuit 522 and transmitting them to sense amplifier band 30; a lower-bit side output buffer OBL for receiving a signal from sense amplifier band 30 in accordance with control signal LC and outputting a data signal to terminal group 4; an upper-bit side input buffer IBU for receiving data signals DQ8 to DQ15 from terminal group 6 in accordance with an upper-bit control signal UC output from control clock generating circuit 522 and transmitting the received signals to sense amplifier band 30; and an upper-bit side output buffer OBU for outputting data read from sense amplifier band 30 to terminal group 6 in accordance with control signal UC.
Generally, in a static random access memory (SRAM), signals supplied from the outside can be easily controlled. Higher packing density of memory cells MC can be achieved by using dynamic memory cells at lower cost as compared with static memory cells. However, since dynamic memory cells hold information by charges accumulated in memory cells, refreshing operation has to be performed every predetermined period, and the control is complicated.
In DRAM 501 shown in FIG. 8, signals supplied from the outside are address signals and control signals similar to those of an SRAM. Consequently, a semiconductor memory of a large capacity, which can be easily controlled is realized by using simple controls supplied from the outside like those in an SRAM and internally using memory cells similar to those in a DRAM.
When a memory cell in the DRAM is not accessed for a predetermined period, however, refreshing is necessary. In a period of time during which an access is not made, refresh trigger generating circuit 16 instructs control clock generating circuit 522 to perform refreshing operation by signal REFCYC.
FIG. 9 is a circuit diagram showing the configuration of sense amplifier band 30 and memory cell MC in FIG. 8.
Referring to FIG. 9, sense amplifier band 30 includes an equalize circuit BEQ, a sense amplifier SAK, and a column selection gate CSG per bit lines BL and ZBL. A memory cell MC is disposed in an intersecting point between a word line WLn provided in corresponding with each memory cell row and bit line BL or ZBL. FIG. 9 shows one memory cell representatively.
Memory cell MC includes an N-channel MOS transistor MT provided between bit line ZBL and a storage node SN and having a gate connected to word line WLn, and a capacitor MQ having one end connected to storage node SN and the other end coupled to a cell plate potential.
Between bit lines BL and ZBL equalize circuit BEQ for equalizing the potential of bit line BL and that of bit line ZBL in accordance with an equalize signal BLEQ is provided.
Equalize circuit BEQ includes three transistors; N-channel MOS transistor which is made conductive according to an equalize signal BLEQ to thereby connect bit lines BL and ZBL, N-channel MOS transistor which is made conductive according to equalize signal BLEQ to couple bit line BL to an equalize potential VBL, and N-channel MOS transistor which is made conductive according to equalize signal BLEQ to couple bit line BL to equalize potential VBL.
Between bit lines BL and ZBL, sense amplifier SAK activated by transistors N3 and P3 which are made conductive according to sense amplifier activating signals S0N and /S0N, respectively, is provided.
Sense amplifier SAK includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1 connected in series between nodes S2P and S2N and each having a gate connected to bit line ZBL, and a P-channel MOS transistor P2 and an N-channel MOS transistor N2 connected in series between nodes S2P and S2N and each having a gate connected to bit line BL.
A connection node of P-channel MOS transistor P1 and N-channel MOS transistor N1 is connected to bit line BL. A connection node of P-channel MOS transistor P2 and N-channel MOS transistor N2 is connected to bit line ZBL. When activated, sense amplifier SAK amplifies the potential difference between bit lines BL and ZBL.
Column selection gate CSG which is made conductive according to a column selection signal CSL generated by a column address is provided for each bit line pair. By column selection gate CSG, bit lines BL and ZBL are connected to global IO lines GIO and ZGIO via local IO lines LIO in a reading or writing mode.
A cycle time of the memory will now be described.
Similar to a DRAM with the complete hidden refresh function, there is a memory what is called a pseudo SRAM having the same control pins as those of an SRAM but not using a time division method different from a DRAM. In the DRAM with the complete hidden refresh function, since the chip itself automatically performs refreshing operation, there is a case that refreshing occurs between (reading/writing) operations. In such a case, the cycle time characteristic deteriorates as compared with a pseudo SRAM having refresh pins.
FIG. 10 is a diagram showing an example of waveforms in the case where refreshing occurs between operations.
Referring to FIG. 10, in cycle #1, operation is switched from NOP (no operation) to READ in response to the rising edge of control signal /OE. FIG. 10 shows a case where a refresh trigger pulse automatically, internally generated competes with operation READ. Operation READ is finished synchronously with the rising edge of control signal /OE and is switched to NOP. Then refreshing is performed internally after completion of operation READ.
In cycle #2, due to designation of writing, control signal /WE changes from the H level to the L level. The signal may be input when the period of refreshing automatically performed internal is finished and the operation is switched again to NOP. The cycle time is therefore limited by a total of the refresh period and the period of reading or writing operation.
In order to prevent deterioration in cycle time characteristics when the refresh competes with operation READ or WRITE, it is very effective to automatically switch the completion of a series of array operations of inactivating a word line, inactivating a sense amplifier, and equalizing the bit lines by a predetermined internally-determined delay time of the DRAM with the complete hidden refresh function without waiting for the rising edge of control signal /OE.
FIG. 11 is an operation waveform chart for explaining the operations in the case where the array operations are completed internally, automatically.
Referring to FIG. 11, in cycle #1, control signal /OE goes low and the operation is switched from NOP to READ. At this time, the refresh trigger pulse competes with the operation READ. Operation READ is switched to operation NOP after delay time TD in which the internal array operations are finished. The switch is made without waiting for the rising edge of control signal /OE. The refreshing operation is finished after delay time TD1, and the operation is switched again to NOP. Then a write instruction can be accepted from the outside. The improved cycle time characteristic as compared with the case shown in FIG. 10 is therefore achieved.
As shown in cycle #2, a writing operation WRITE starts in response to the rising edge of control signal /WE. The operation is switched to NOP after elapse of delay time TD3. The switch is also internally, automatically made without waiting for the rising edge of control signal /WE.
As described above, in the case where the array operations are automatically completed in a delay time internally determined, the array operations are performed only in the minimum time, so that the improved cycle time characteristic as compared with the case of instructing completion of the array operations from the outside is achieved. Since the array operations are internally, automatically completed, however, a problem such that it becomes very difficult to evaluate a restoring characteristic (interval in which data can be rewritten into an array in a reading mode) occurs.
FIG. 12 is an operational waveform chart for explaining the access time of the memory.
Referring to FIG. 12, the access time of the memory is determined by times T11 to T15.
Time T11 is a period of time from completion of equalize operation according to the falling edge of equalize signal BLEQ to the instance when word line WL is made active.
Time T12 is a period of time from an instance when word line WL is made active to an instance when the sense amplifier is activated synchronously with the rising edge of control signal ZS0S.
Time T13 is a period of time from an instance when the sense amplifier is activated until the word line WL is made inactive.
Time T14 is a period of time from an instance when the word line is made inactive to an instance when the sense amplifier is made inactive.
Time T15 is a period of time from an instance when the sense amplifier is made inactive to an instance when the bit line pair is equalized again.
For the sake of stable operation, the longer each of the times T11 to T15 is, the better. However, for higher processing speed of the memory, it is necessary to shorten each time as much as possible. Consequently, it is important to grasp the margin of each time of the developed memory.
In the DRAM with the complete hidden refresh function, however, as described with reference to FIG. 11, operation READ is switched in delay time TD2 internally determined. Consequently, the operation limit cannot be evaluated in accordance with the control signal supplied from the outside. Therefore, it is difficult to evaluate the characteristics of the developed memory.
An object of the invention is to provide a semiconductor memory device capable of controlling the timing of an array operation in response to a trigger signal in a test mode and easily evaluating a restoring characteristic.
The invention is directed to, in short, a semiconductor memory device having a test mode and a normal mode as operation modes, and including a memory array, a plurality of word lines, a row decoding circuit, a plurality of bit line pairs, a sense amplifier circuit, and a timing control circuit.
The memory array includes a plurality of memory cells arranged in a matrix of rows and columns. The plurality of word lines are used to select a row of memory cells. The row decoding circuit activates a word line corresponding to an address signal out of the plurality of word lines in response to a word line activating signal. The plurality of bit line pairs is provided in correspondence with columns of the memory cells. The sense amplifier circuit for amplifies data held in the plurality of memory cells read on the plurality of bit line pairs in accordance with a sense amplifier activating signal.
The timing control circuit outputs the word line activating signal and the sense amplifier activating signal in accordance with an external control signal in the normal mode. The timing control circuit makes a phase relation between the word line activating signal and the sense amplifier activating signal different from that in the normal mode and outputs the resultant phase relation in response to a timing test signal supplied from the outside in the test mode.
A main advantage of the invention is, therefore, that a margin of a timing of making the word line active or inactive and a margin of a timing of making the sense amplifier active or inactive whose operation margins cannot be recognized in the normal operation can be evaluated.
The foregoing and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.